SEU Mitigation Testing of Xilinx Virtex II FPGAs
نویسندگان
چکیده
SRAM-based reconfigurable programmable logic is widely used in commercial applications and occasionally used in space flight applications because of its susceptibility to singleevent upset (SEU). Upset detection and mitigation schemes have been tested on the Xilinx Virtex II X-2V1000 in heavy-ion and proton irradiation to control the accumulation of SEUs and to mitigate their effects on the intended operation. Non-intrusive upset detection and partial reconfiguration in combination with TMR can repair the design to maintain state information. Inbeam results on a simple test design demonstrate the effectiveness of these methods when used together.
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